It is known that for the manufacturing of these memory devices it is necessary to provide for layers of different of different thickness in the active areas of the devices forming the memory cells.
For forming such oxide layers, a selective removal of the different layers that are successively grown in the active areas is necessary. To this purpose, several chemical etching processes are performed to remove the unnecessary layers from the silicon surface.
Examples of electrically programmable non-volatile memory cells are the double polysilicon level (DP) FLOTOX EEPROM memory cells, one of which is shown in FIGS. 1 and 2 and includes a floating-gate MOS transistor 2 and a selection MOSFET 3. The floating-gate MOS transistor 2 comprises an N type source region 4 and an N type drain region 5 both formed in a P type semiconductor substrate or well 6, spaced apart from each other. The portion of P type substrate or well comprised between the source and drain regions 4 and 5 forms a channel region, and a floating gate electrode 7 (formed in a first polysilicon level) is placed over the channel region and part of the drain region 5, with the interposition of a gate oxide layer 8 having typically a thickness of 200 .ANG.. At the drain region 5, the gate oxide 8 has a thinner portion 9, with typical thickness of about 70 .ANG., called tunnel oxide. The drain region 5 comprises, under the tunnel oxide 9, a region 10 heavily doped of the N type. A control gate electrode 11 (formed in a second polysilicon level) is placed over the floating gate electrode 7 with the interposition of a dielectric layer 100.
The selection MOSFET 3 of each memory cell is connected in series to the respective floating-gate MOS transistor 2, and comprises an N type source region coincident with the drain region 5 of the floating-gate MOS transistor 2, and an N type drain region 12 formed in the P type substrate or well 6. The region of the substrate or well 6 comprised between the drain region 12 and the source region 5 of MOSFET 3 forms a channel region, over which two polysilicon electrodes 13, 14 are placed, forming the gate of MOSFET 3. The first electrode 13 is separated from the channel region by a gate oxide layer 80. The second electrode 14 is separated from the first electrode 13 by a dielectric layer 101.
Conventionally, as far as the selection transistors 3 are concerned, the two polysilicon electrodes 13, 14 belong to respective lines formed from the first and the second polysilicon levels, and said lines are electrically short-circuited in a region of the array not shown in FIG. 1.
The oxide layer 80 is generally thicker than the oxide layer 8 (typically the oxide layer 80 is 300 .ANG. thick), since the former must be capable of sustaining the voltages involved in the process of programming the memory cells, voltages which are higher than the supply voltage.
With reference to FIGS. 3 to 6, the conventional process for the fabrication of an EEPROM memory device includes using FLOTOX EEPROM memory cells and MOSFETs 90 for the circuitry. The process provides for defining active areas for the memory cells and the MOSFETs of the circuitry; the formation of a sacrificial oxide layer; the implantation of an N type dopant for forming the regions 10 of the memory cells, and a thermal diffusion process for diffusing the dopant; and the subsequent removal of the sacrificial oxide.
By means of a thermal oxidation a first gate oxide layer 15 is formed, having a thickness of about 200 .ANG.. The oxide layer 15 is formed over the active areas of both the memory cells 1 and the MOSFETs 90 of the circuitry (FIG. 3).
By means of a conventional photolithographic process, providing for the deposition of a photoresist 16 and the selective etching thereof, the first oxide layer 15 is removed from the active area region wherein the floating-gate MOSFET 2 will be formed, and from the active areas where low-voltage (LV) transistors 90 of the circuitry will be formed (FIG. 4).
By means of thermal oxidation a second gate oxide layer 800 is formed having a thickness of about 170 .ANG.. By means of a conventional photolithographic technique, providing for the deposition of another photoresist layer 17 and the selective etching thereof, the second oxide layer 800 is selectively removed from the tunnel region of the memory cell (FIG. 5). By means of a further thermal oxidation the tunnel oxide layer 9 is formed, having a typical thickness of about 70 .ANG..
The memory cell 1 and the MOSFETs 90 of the circuitry are then conventionally completed by defining their gates, forming the source and drain regions, forming insulating spacers, and so on.
As it will be appreciated, the gate oxide layer 80 of the selection MOSFET 3, as well as the gate oxide layer of the high-voltage (HV) MOSFETs of the circuitry that, as the selection MOSFET 3 have to sustain the high voltages involved in the programming operation, is formed by a stack of the three oxide layers 15, 800 and 9. The gate oxide layer 8 of the floating-gate MOS transistor 2, as well as the gate oxide layer of the low-voltage (LV) MOSFETs of the circuitry is instead formed by a stack of the two oxide layers 800 and 9.
A drawback of this process is due to the fact that the surface of the silicon where the tunnel oxide 9 is grown is affected by the removal of the first and second oxide layers. The twice removal increases the probability of damaging the silicon surface, negatively affecting the reliability of the tunnel oxide subsequently grown, and thus negatively affecting the reliability of the memory device.